1. Field of the Invention
Example embodiments of the present invention relate generally to a semiconductor device, a parallel interface system and methods thereof, and more particularly to a semiconductor device, a parallel interface system and methods of reducing skew.
2. Description of the Related Art
Data transmission rates between semiconductor devices (e.g., between a dynamic random access memory (DRAM) device and a central processing unit (CPU) or a controller) may be limited by a time jitter of a phase locked loop (PLL)/delayed locked loop (DLL), an offset caused by a fabrication error in a transmitter and/or a receiver, interference between transmission signals in a transmission channel, etc.
In parallel interface systems, a parallel data signal and a reference clock signal may be transmitted to a receiver in synchronization with a sampling clock signal of a transmitter. However, due to factors limiting the data transmission rate, a difference in channel time between the reference clock signal and the data signal and/or between data signals may occur if a skew occurs (e.g., because the data transmission rate increases between semiconductor devices). The skew may indicate a phase difference between the reference clock signal and the parallel data signal.
As the skew increases, a voltage margin and a time margin of a transmission data signal may be reduced. If the time margin is reduced, an “indefinite” portion of data may increase (e.g., a metastable data state of the transmission data signal), and it may be more difficult to secure a sufficient setup/hold time. In order to enable a semiconductor device receiving a parallel data signal to correctly identify the data signal, a sampling clock of the receiving semiconductor device may be set to increase the voltage margin and the time margin.
In an example, a synchronous process may be used to set the sampling clock in a parallel interface system. In the conventional synchronizing process, a data signal and a reference clock signal may be separately transmitted to a semiconductor device and the semiconductor device may identify the data signal. However, if a data transmission line is not matched with a reference clock transmission line in the conventional synchronizing process, skew may occur between the data signal and the reference clock signal. Accordingly, it may be difficult to accomplish higher-rate data signal transmission.
FIG. 1A is a timing chart of a reference clock signal CLKref and N parallel data bit signals DQ1 through DQN output from a transmitter within a conventional parallel interface system. FIG. 1B is a timing chart of a reference clock signal CLKref and N parallel data bit signals DQ1′ through DQN′ input to a receiver within a conventional parallel interface system.
Referring to FIGS. 1A and 1B, the transmitter may transmit the reference clock signal TXCLKref and the N parallel data bit signals DQ1 through DQN to the receiver in response to a transmitting sampling clock signal TXCLK. The receiver may generate a receiving data sampling clock signal CLKda whose phase may be different from that of the received reference clock signal CLKref by a half period. The receiver may sample the received N parallel data bit signals DQ1′ through DQN′ in response to the receiving data sampling clock signal CLKda. If data transmission lines are not matched with a reference clock transmission line, a timing error (e.g., a phase skew) may occur between the receiving reference clock signal RXCLKref and each signal (e.g., DQ1′) of the N parallel data bit signals DQ1′ through DQN′, as illustrated in FIG. 1B. Accordingly, the receiving data sampling clock signal CLKda may be displaced from a position associated with a theoretical “maximum” time margin. As a result, the time margin and the voltage margin of the N parallel data bit signals DQ1′ through DQN′ may be reduced.
Referring to FIGS. 1A and 1B, the receiving data sampling clock signal CLKda may be set to provide a higher (e.g., maximum) time margin by performing per-pin deskew process using clock and data recovery (CDR). In the per-pin deskew process CDR, a data signal transmitted per data pin may be oversampled (e.g., two or more times) during a single signal period and a position or phase of the receiving data sampling clock signal CLKda may be extracted based on the values of sampled data signals.
FIGS. 2A through 2C are conceptual diagrams illustrating the conventional per-pin deskew process using CDR. Referring to FIGS. 2A through 2C, the phase of an edge sampling clock CLKed may be different from the phase of a data sampling clock signal CLKda by a half period of the phase of a data signal. The edge sampling clock CLKed may be used to detect edge information in the data signal and the data sampling clock signal CLKda may be used to identify the data signal (e.g., as one of a first logic level, such as a higher logic level or logic “1”, and a second logic level, such as a lower logic level or logic “0”).
In particular, FIG. 2A illustrates the data sampling clock signal CLKda positioned so as to provide a theoretical maximum time margin, while FIGS. 2B and 2C illustrate conditions where the position of the data sampling clock signal CLKda introduces skew.
Referring to FIGS. 2B and 2C, in order to adjust the position of the data sampling clock signal CLKda so as to match the time margin of FIG. 2A, the data sampling clock signal CLKda may be shifted to the “left” in FIG. 2B and to the “right” in FIG. 2C. The per-pin deskew process using CDR may allow a sampling clock signal to track the changes of a data signal so as to maintain a sampling position approximately at the maximum time margin (e.g., see FIG. 2A) even while data is being transmitted. Accordingly, even if a skew occurs between a data signal and a sampling clock signal (e.g., due to the change of temperature or voltage) while data is being transmitted, the per-pin deskew process using CDR may reduce the skew.
However, the per-pin deskew process using CDR may require an additional sampling clock signal (e.g., the edge sampling clock CLKed) for detecting edge information in the data signal, a receiving circuit for receiving information relating to a phase skew between the data signal and the data sampling clock signal CLKda, and a phase control circuit for changing the position of the data sampling clock signal CLKda (e.g., so as to maintain the maximum time margin). Thus, an area occupied by a circuit for reducing skew may be increased, as well as manufacturing costs. Accordingly, it may be difficult to employ the per-pin deskew process using CDR in parallel data transmission of conventional semiconductor (e.g., dynamic random access memory (DRAM)) devices.
Another conventional process for reducing skew between a data signal and a data sampling clock signal may be a per-pin deskew process using training data. Unlike the conventional per-pin deskew process using CDR, the per-pin deskew process using training data need not include an additional circuit for edge detection in a semiconductor device (e.g., a DRAM device) receiving the data signal.
FIG. 3 is a conceptual diagram illustrating the conventional per-pin deskew process using training data. Referring to FIG. 3, in a conventional parallel interface system, a transmitting semiconductor device (e.g., a controller) may transmit given pattern data referred to as “training data”. The transmitting semiconductor device may receive the training data back from the receiving semiconductor device in synchronization with receiving sampling clock signals S1 through S13 having different phases. The transmitting semiconductor device may compare the transmitted training data with the received training data and may determine whether a reception error has occurred based on a result of the comparison.
Referring to FIG. 3, a reception error may occur if the training data is received in synchronization with the receiving sampling clock signals S1 through S3 and S11 through S13. An optimum phase (e.g., a phase having a least probability of error) of a receiving sampling clock signal for the transmitting semiconductor device may be determined based on the determination on the reception error. In other words, the phase of the receiving sampling clock signal S7 having a least probability of error occurrence may be obtained with phase information of the receiving sampling clock signals S4 through S10 in which an error does not occur.
Referring to FIG. 3, phase information may be obtained per data pin in parallel data transmitted by the transmitting semiconductor device using the above-described process. The phase of a receiving sampling clock signal corresponding to each data pin may be controlled based on the phase information. The phase of a transmitting sampling clock signal of the transmitting semiconductor device may be controlled in the same manner.
However, the per-pin deskew process using training data may take a longer period of time to perform as compared to the per-pin deskew process using CDR. Thus, if the per-pin deskew process using training data is performed frequently, system performance may be reduced. Accordingly, in determining whether to use the per-pin deskew process using either training data or CDR data, a system designer may be required to make a trade-off by choosing between the increased occupied chip area allocated to circuitry associated with the per-pin deskew process using CDR data and the decreased performance levels of the per-pin deskew process using training data.